STAMP-Software Architecture


 

Introduction

Here is the structure of the firmware I have written. The complete software is written in C-language. And is divided into different modules which represent a higher or lower abstraction level. Main parts of the code is my own code. The ATA/IDE-code I took from other pojects/persons, but found out that this code has not that optimum to run with this processor, so I wrote this codefragment totally new.
I hope the following figures are interesting for you. If you have question belonging to a detailled PEC- or INT-dataflow, please eMail me and I will publish more information on this site.

Block Diagram

The picture below shows the block diagram of the SW-architecture and abstraction layers between high-level and HW-based modules. The main MP3 dataflow is done by two PEC-transfers (see purple arrows).
The red arrows of each module show you, which modul can cause an interrupt. If such an interrupt appears, the endless loop of the MMI-modul registers that and reacts with the corresponding action.

Memory Organization

This is next interesting point, because the 80c16x supports special access to its internal registers. This access is done with an ordinary memory read/write operation. So the registers are memory mapped and hide some Flash-ROM or RAM-areas, which you can't use any more.
Furthermore, all external devices are attached via chip select-lines and are memory mapped into the full adressregion of the 80c16x.
The next figure shows you how the memory-organization is held in the STAMP-project, and which parts are based on external devices.
Regarding to PEC-transfers: The PEC-transfers work only within the 1st 64 KB block. I solved this restriction with the following memory-organization:

PEC-Transfers and Interrupt-Handling

I have implemented a lot of interrupt routines and PEC-transfers. It is possible to avoid them, but there are a lot of advantages.
A PEC-transfer is nearly the same than a DMA-transfer of the common CPU-systems. The most difference is, that each byte- or word-transfer should be initiated by a "hidden interrupt". But the transfer of the byte/word will be done without fetching new opcode from flash. Even if the belonging interrupt appears the opcode for that transfer-operation is injected into the prefetch-pipeline of the CPU. So no special time to fetch new code, and clearing of the pipeline is necessary. This important behaviour of the CPU makes these PEC-transfers so fast. The so called "hidden interrupt" also does not need a interrupt service routine, because the action for that interrupt is the PEC-transfer.
The interrupt-sources to initiate the transfer from IDE to RAM-buffer is done by a timer and the transfer from that buffer to the Decoder-IC is initiated by a SSC-Interrupt every time the SSC-output-buffer runs empty.

Tool Chain

I am using an older version of the Tasking C166 compiler. An alternativ is the compiler from Keil, but I have never used a compiler from them. The Tasking compiler is in the first step very crude but it's working and supports all professional functionality.
Both compiler-versions are available for free via download at the companies internet pages (see my link-page). They have some limits, but for the first project they should work.

On the other hand I am using a very old multi- or voltmeter. One time I have lend out an Osscilloscope, but thats all.

The PCB-design was done with an older Protel -version. I have had some experience with that. But the Eagle-versions are also very useful, because for this PCB-size the SW is for free and is very common.

 


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For problems or questions regarding this web contact Christoph. Last updated: 27/04/03.